Web3 Jobs in Sacramento, California, United States

• Digital Backend/Mixed Signal Design Flow setup and maintenance.
• Backend Implementation (RTL to GDS).
• Library Characterization.
• SPICE simulations.

Qualifications:

• 12+ years experience in driving Tape-out of complex SOC/ASICs.
• Experience in implementing low-power designs on advanced foundry nodes (TSMC/Samsung/GF/Intel).
• Hands-on experience in RTL to GDS flows or methodologies.
• Experience in multiple EDA tools relevant to place and route, STA, Physical verification, Power grid verification, synthesis, DFT, and LP checks.
• Experience with CMOS digital logic function, timing, and power.
• Experience with circuit design flows.

Preferred Qualifications:

• Experience leading one or more aspects of physical design or physical design flow/methodology to successful tapeouts and shipping silicon.
• Experience in extraction of design parameters, QoR metrics, and analysing trends and knowledge of semiconductor device physics and transistor characteristics.
• Experience in IP design and integration.
• Knowledge of semiconductor device physics, transistor characteristics and multiple foundry.